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application note ds042 (v1.3) october 9, 2000 www.xilinx.com 1 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. features ? industry's first totalcmos? pld - both cmos design and process technologies fast zero power (fzp?) design technique provides ultra-low power and very high speed 5v, in-system programmable (isp) using a jtag interface - on-chip supervoltage generation - isp commands include: enable, erase, program, verify - supported by multiple isp programming platforms - four pin jtag interface (tck, tms, tdi, tdo) - jtag commands include: bypass, idcode high speed pin-to-pin delays of 7.5 ns ultra-low static power of less than 100 a 100% routable with 100% utilization while all pins and all macrocells are fixed deterministic timing model that is extremely simple to use up to 20 clocks available support for complex asynchronous clocking innovative xpla? architecture combines high speed with extreme flexibility 1000 erase/program cycles guaranteed 20 years data retention guaranteed logic expandable to 37 product terms pci compliant advanced 0.5 e 2 cmos process security bit prevents unauthorized access design entry and verification using industry standard and xilinx cae tools reprogrammable using industry standard device programmers innovative control term structure provides either sum terms or product terms in each logic block for: - programmable 3-state buffer - asynchronous macrocell register preset/reset - up to two asynchronous clocks programmable global 3-state pin facilitates `bed of nails' testing without using logic resources available in tqfp and lqfp packages available in both commercial and industrial grades description the xcr5128c cpld (complex programmable logic device) is a member of the coolrunner ? family of cplds from xilinx. these devices combine high speed and zero power in a 128 macrocell cpld. with the fzp design tech- nique, the xcr5128c offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 a at standby without the need for ? turbo bits ? or other power down schemes. by replacing conventional sense amplifier methods for implementing product terms (a tech- nique that has been used in plds since the bipolar era) with a cascaded chain of pure cmos gates, the dynamic power is also substantially lower than any competing cpld. these devices are the first totalcmos plds, as they use both a cmos process technology and the pat- ented full cmos fzp design technique. the xilinx fzp cplds utilize the patented xpla (extended programmable logic array) architecture. the xpla architecture combines the best features of both pla and pal type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. the xpla structure in each logic block provides a fast 7.5 ns pal path with five dedicated product terms per output. this pal path is joined by an additional pla structure that deploys a pool of 32 product terms to a fully programmable or array that can allocate the pla product terms to any output in the logic block. this combination allows logic to be allocated effi- ciently throughout the logic block and supports as many as 37 product terms on an output. the speed with which logic is allocated from the pla array to an output is only 2ns, regardless of the number of pla product terms used, which results in worst case t pd 's of only 9.5 ns from any pin to any other pin. in addition, logic that is common to multiple out- puts can be placed on a single pla product term and shared across multiple outputs via the or array, effectively increasing design density. the xcr5128c cplds are supported by industry standard cae tools (cadence/orcad, exemplar logic, mentor, synopsys, synario, viewlogic, and synplicity), using text (abel, vhdl, verilog) and/or schematic entry. design ver- ification uses industry standard simulators for functional and timing simulation. development is supported on per- sonal computer, sparc, and hp platforms. device fitting uses xilinx developed tools including webfitter. the xcr5128c cpld is electrically reprogrammable using industry standard device programmers from vendors 0 xcr5128c: 128 macrocell cpld with enhanced clocking ds042 (v1.3) october 9, 2000 014* product specification r ds042.fm page 1 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking ds042 (v1.3) october 9, 2000 www.xilinx.com 2 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. such as data i/o, bp microsystems, sms, and others. the xcr5128c also includes an industry-standard, ieee 1149.1, jtag interface through which in-system program- ming (isp) and reprogramming of the device are sup- ported. xpla architecture figure 1 shows a high level block diagram of a 128 macro- cell device implementing the xpla architecture. the xpla architecture consists of logic blocks that are interconnected by a zero-power interconnect array (zia). the zia is a vir- tual crosspoint switch. each logic block is essentially a 36v16 device with 36 inputs from the zia and 16 macro- cells. each logic block also provides 32 zia feedback paths from the macrocells and i/o pins. from this point of view, this architecture looks like many other cpld architectures. what makes the coolrunner family unique is what is inside each logic block and the design technique used to implement these logic blocks. the contents of the logic block will be described next. logic block i/o 36 16 16 36 16 16 mc1 mc2 mc16 i/o mc1 mc2 mc16 logic block i/o 36 16 16 36 16 16 mc1 mc2 mc16 i/o mc1 mc2 mc16 zia logic block logic block logic block i/o 36 16 16 36 16 16 mc1 mc2 mc16 i/o mc1 mc2 mc16 logic block logic block i/o 36 16 16 36 16 16 mc1 mc2 mc16 i/o mc1 mc2 mc16 sp00464 logic block figure 1: xilinx xpla cpld architecture ds042.fm page 2 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking 3 www.xilinx.com ds042 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. logic block architecture figure 2 illustrates the logic block architecture. each logic block contains control terms, a pal array, a pla array, and 16 macrocells. the six control terms can individually be configured as either sum or product terms, and are used to control the preset/reset and output enables of the 16 macrocells ? flip-flops. in addition, two of the control terms can be used as clock signals (see macrocell archi- tecture section for details). the pal array consists of a pro- grammable and array with a fixed or array, while the pla array consists of a programmable and array with a pro- grammable or array. the pal array provides a high speed path through the array, while the pla array provides increased product term density. each macrocell has five dedicated product terms from the pal array. the pin-to-pin t pd of the xcr5128c device through the pal array is 7.5 ns. if a macrocell needs more than five product terms, it simply gets the additional product terms from the pla array. the pla array consists of 32 product terms, which are available for use by all 16 macro- cells. the additional propagation delay incurred by a mac- rocell using one or all 32 pla product terms is just 2 ns. so the total pin-to-pin t pd for the xcr5128c using six to 37 product terms is 9.5 ns (7.5 ns for the pal + 2 ns for the pla). ds042.fm page 3 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking ds042 (v1.3) october 9, 2000 www.xilinx.com 4 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. figure 2: xilinx xpla logic block architecture to 16 macrocells 6 5 control pal array 36 zia inputs pla array (32) sp00435a ds042.fm page 4 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking 5 www.xilinx.com ds042 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. macrocell architecture figure 3 shows the architecture of the macrocell used in the coolrunner xcr5128c. the macrocell can be config- ured as either a d- or t-type flip-flop or a combinatorial logic function. a d-type flip-flop is generally more useful for implementing state machines and data buffering while a t-type flip-flop is generally more useful in implementing counters. each of these flip-flops can be clocked from any one of six sources. four of the clock sources (clk0, clk1, clk2, clk3) are connected to low-skew, device-wide clock networks designed to preserve the integrity of the clock signal by reducing skew between rising and falling edges. clock 0 (clk0) is designated as a ? synchronous ? clock and must be driven by an external source. clock 1 (clk1), clock 2 (clk2), and clock 3 (clk3) can be used as ? synchronous ? clocks that are driven by an external source, or as ? asynchronous ? clocks that are driven by a macrocell equation. clk0, clk1, clk2 and clk3 can clock the macrocell flip-flops on either the rising edge or the falling edge of the clock signal. the other clock sources are two of the six control terms (ct2 and ct3) provided in each logic block. these clocks can be individually configured as either a product term or sum term equation created from the 36 signals available inside the logic block. the tim- ing for asynchronous and control term clocks is different in that the t co time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the t su time is reduced. the six control terms of each logic block are used to control the asynchronous preset/reset of the flip-flops and the enable/disable of the output buffers in each macrocell. control terms ct0 and ct1 are used to control the asyn- chronous preset/reset of the macrocell's flip-flop. note that the power-on reset leaves all macrocells in the ? zero ? state when power is properly applied, and that the pre- set/reset feature for each macrocell can also be disabled. control terms ct2 and ct3 can be used as a clock signal to the flip-flops of the macrocells, and as the output enable of the macrocell's output buffer. control terms ct4 and ct5 can be used to control the output enable of the mac- rocell's output buffer. having four dedicated output enable control terms ensures that the coolrunner devices are pci compliant. the output buffers can also be always enabled or always disabled. all coolrunner devices also provide a global 3-state (gts) pin, which, when enabled and pulled low, will 3-state all the outputs of the device. this pin is provided to support ? in-circuit testing ? or ? bed-of-nails tes ti ng ? . there are two feedback paths to the zia: one from the macrocell, and one from the i/o pin. the zia feedback path before the output buffer is the macrocell feedback path, while the zia feedback path after the output buffer is the i/o pin feedback path. when the macrocell is used as an out- put, the output buffer is enabled, and the macrocell feed- back path can be used to feedback the logic implemented in the macrocell. when the i/o pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the zia via the i/o feedback path, and the logic imple- mented in the buried macrocell can be fed back to the zia via the macrocell feedback path. it should be noted that unused inputs or i/os should be properly terminated (see the section on terminations in this data sheet and the appli- cation note terminating unused i/o pins in xilinx xpla1 and xpla2 coolrunner cplds ). init (p or r) d/t q sp00558 clk0 clk0 clk1 clk1 to zia gnd ct0 ct1 gts ct2 ct3 ct4 ct5 v gnd cc gnd pal pla clk2 clk2 clk3 clk3 figure 3: xcr5128c macrocell architecture ds042.fm page 5 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking ds042 (v1.3) october 9, 2000 www.xilinx.com 6 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. simple timing model figure 4 shows the coolrunner timing model. the cool- runner timing model looks very much like a 22v10 timing model in that there are three main timing parameters, including t pd , t su , and t co . in other competing architec- tures, the user may be able to fit the design into the cpld, but is not sure whether system timing requirements can be met until after the design has been fit into the device. this is because the timing models of competing architectures are very complex and include such things as timing depen- dencies on the number of parallel expanders borrowed, sharable expanders, varying number of x and y routing channels used, etc. in the xpla architecture, the user knows up front whether the design will meet system timing requirements. this is due to the simplicity of the timing model. output pin input pin sp00552 t pd_pal = combinatorial pal only t pd_pla = combinatorial pal + pla output pin input pin dq registered t su_pal = pal only t su_pla = pal + pla registered t co global clock pin figure 4: coolrunner timing model ds042.fm page 6 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking 7 www.xilinx.com ds042 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. totalcmos design technique for fast zero power xilinx is the first to offer a totalcmos cpld, both in pro- cess technology and design technique. xilinx employs a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate implementation allows xilinx to offer cplds which are both high performance and low power, breaking the para- digm that to have low power, you must have low perfor- mance. refer to figure 5 and tab le 1 showing the i cc vs. frequency of our xcr5128c totalcmos cpld (data taken w/eight up/down, loadable 16 bit counters at 5v, 25 c). table 1: v cc vs. frequency (v cc = 5.v, 25 c) frequency (mhz)0 1 20406080100120 typical i cc (ma) 0.048 1.281 23.55 46.93 70.05 92.45 114.4 136.2 frequency (mhz) sp00617 120406080100 0 20 40 60 80 120 i cc (ma) 100 120 140 figure 5: i cc vs. frequency at v cc = 5.0v, 25 c ds042.fm page 7 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking ds042 (v1.3) october 9, 2000 www.xilinx.com 8 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. jtag testing capability jtag is the commonly-used acronym for the boundary scan test (bst) feature defined for integrated circuits by ieee standard 1149.1. this standard defines input/output pins, logic control functions, and commands which facilitate both board and device level testing without the use of spe- cialized test equipment. the xilinx xcr5128c devices use the jtag interface for in-system programming/repro- gramming. although only a subset of the full jtag com- mand set is implemented (see tab le 4 ), the devices are fully capable of sitting in a jtag scan chain. the xilinx xcr5128c ? s jtag interface includes a tap port defined by the ieee 1149.1 jtag specification. as imple- mented in the xilinx xcr5128c, the tap port includes four of the five pins (refer to ta ble 2 ) described in the jtag specification: tck, tms, tdi, and tdo. the fifth signal defined by the jtag specification is trst* (test reset). trst* is considered an optional signal, since it is not actu- ally required to perform bst or isp. the xilinx xcr5128c saves an i/o pin for general purpose use by not implement- ing the optional trst* signal in the jtag interface. instead, the xilinx xcr5128c supports the test reset func- tionality through the use of its power up reset circuit, which is included in all xilinx cplds. the pins associated with the tap port should connect to an external pull-up resistor to keep the jtag signals from floating when they are not being used. in the xilinx xcr5128c, the four mandatory jtag pins each require a unique, dedicated pin on the device. the devices come from the factory with these i/o pins set to perform jtag functions, but through the software, the final function of these pins can be controlled. if the end applica- tion will require the device to be reprogrammed at some future time with isp, then the pins can be left as dedicated jtag functions, which means they are not available for use as general purpose i/o pins. however, unlike competing cplds, the xilinx xcr5128c allow the macrocells associ- ated with these pins to be used as buried logic when the jtag/isp function is enabled. this is the default state for the software, and no action is required to leave these pins enabled for the jtag/isp functions. if, however, jtag/isp is not required in the end application, the software can specify that this function be turned off and that these pins be used as general purpose i/o. because the devices ini- tially have the jtag/isp functions enabled, the jedec file can be downloaded into the device once, after which the jtag/isp pins will become general purpose i/o. this fea- ture is good for manufacturing because the devices can be programmed during test and assembly of the end product and yet still use all of the i/o pins after the programming is done. it eliminates the need for a costly, separate program- ming step in the manufacturing process. of course, if the jtag/isp function is never required, this feature can be turned off in the software and the device can be pro- grammed with an industry-standard programmer, leaving the pins available for i/o functions. ta b l e 3 defines the ded- icated pins used by the four mandatory jtag signals for each of the xcr5128c package types. table 2: jtag pin description pin name description tck test clock output clock pin to shift the serial data and instructions in and out of the tdi and tdo pins, respectively. tms test mode select serial input pin selects the jtag instruction mode. tms should be driven high during user mode operation. tdi test data input serial input pin for instructions and test data. data is shifted in on the rising edge of tck. tdo test data output serial output pin for instructions and test data. data is shifted out on the falling edge of tck. the signal is tri-stated if data is not being shifted out of the device. table 3: xcr5128c jtag pinout by package type device xcr5128c (pin number / macrocell #) tck tms tdi tdo 100-pin vqfp 62/f15 15/c15 4/b15 73/g15 128-pin tqfp 82/f15 21/c15 8/b15 95/g15 ds042.fm page 8 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking 9 www.xilinx.com ds042 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. 5v, in-system programming (isp) isp is the ability to reconfigure the logic and functionality of a device, printed circuit board, or complete electronic sys- tem before, during, and after its manufacture and shipment to the end customer. isp provides substantial benefits in each of the following areas: design - faster time-to-market - debug partitioning and simplified prototyping - printed circuit board reconfiguration during debug - better device and board level testing manufacturing - multi-functional hardware - reconfigurability for test - eliminates handling of ? fine lead-pitch ? components for programming - reduced inventory and manufacturing costs - improved quality and reliability field support - easy remote upgrades and repair - support for field configuration, re-configuration, and customization the xilinx xcr5128c allows for 5v, in-system program- ming/reprogramming of its eeprom cells via its jtag interface. an on-chip charge pump eliminates the need for externally-provided supervoltages, so that the xcr5128c may be easily programmed on the circuit board using only the 5v supply required by the device for normal operation. a set of low-level isp basic commands implemented in the xcr5128c enable this feature. the isp commands imple- mented in the xilinx xcr5128c are specified in tab le 5 please note that an enable command must precede all isp commands unless an enable command has already been given for a preceding isp command. terminations the coolrunner xcr5128c cplds are totalcmos devices. as with other cmos devices, it is important to consider how to properly terminate unused inputs and i/o pins when fabricating a pc board. allowing unused inputs and i/o pins to float can cause the voltage to be in the lin- ear region of the cmos input structures, which can increase the power consumption of the device. the xcr5128c cplds have programmable on-chip pull-down resistors on each i/o pin. these pull-downs are automati- cally activated by the fitter software for all unused i/o pins. note that an i/o macrocell used as buried logic that does not have the i/o pin used for input is considered to be unused, and the pull-down resistors will be turned on. xilinx recommends that any unused i/o pins on the xcr5128c device be left unconnected. there are no on-chip pull-down structures associated with the dedicated input pins. xilinx recommends that any unused dedicated inputs be terminated with external 10k ? pull-up resistors. these pins can be directly connected to v cc or gnd, but using the external pull-up resistors main- tains maximum design flexibility should one of the unused dedicated inputs be needed due to future design changes. when using the jtag/isp functions, it is also recom- mended that 10k ? pull-up resistors be used on each of the pins associated with the four mandatory jtag signals. let- ting these signals float can cause the voltage on tms to come close to ground, which could cause the device to enter jtag/isp mode at unspecified times. see the appli- cation notes jtag and isp overview for xilinx xpla1 and xpla2 cplds and terminating unused i/o pins in xilinx xpla1 and xpla2 coolrunner cplds for more informa- tion. table 4: xcr5128c low-level jtag boundary-scan commands instruction (instruction code) register used description bypass (1111) bypass register places the 1 bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through the selected device to adjacent devices during normal device operation. the bypass instruction can be entered by holding tdi at a constant high value and completing an instruction-scan cycle. idcode (0001) boundary-scan register selects the idcode register and places it between tdi and tdo, allowing the idcode to be serially shifted out of tdo. the idcode instruction permits blind interrogation of the components assembled onto a printed circuit board. thus, in circumstances where the component population may vary, it is possible to determine what components exist in a product. ds042.fm page 9 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking ds042 (v1.3) october 9, 2000 www.xilinx.com 10 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. jtag and isp interfacing a number of industry-established methods exist for jtag/isp interfacing with cpld ? s and other integrated cir- cuits. the xilinx xcr5128c supports the following meth- ods: pc parallel port workstation or pc serial port embedded processor automated test equipment third party programmers high-end isp tools for more details on jtag and isp for the xcr5128c, refer to the related application note: jtag and isp overview for xilinx xpla1 and xpla2 cplds . table 5: low level isp commands instruction (register used) instruction code description enable (isp shift register) 1001 enables the erase, program, and verify commands. erase (isp shift register) 1010 erases the entire eeprom array. program (isp shift register) 1011 programs the data in the isp shift register into the addressed eeprom row. verify (isp shift register) 1100 transfers the data from the addressed row to the isp shift register. table 6: programming specifications symbol parameter min. max. unit dc parameters v ccp v cc supply program/verify 4.5 5.5 v i ccp i cc limit program/verify 200 ma v ih input voltage (high) 2.0 v v il input voltage (low) 0.8 v v sol output voltage (low) 0.5 v v soh output voltage (high) 2.4 v tdo_i ol output current (low) 12 ma tdo_i oh output current (high) -12 ma ac parameters f max tck maximum frequency 10 mhz pwe pulse width erase 100 ms pwp pulse width program 10 ms pwv pulse width verify 10 s init initialization time 100 s tms_su tms setup time before tck 10 ns tdi_su tdi setup time before tck 10 ns tms_h tms hold time after tck 20 ns tdi_h tdi hold time after tck 20 ns tdo_co tdo valid after tck 30 ns ds042.fm page 10 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking 11 www.xilinx.com ds042 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. absolute maximum ratings 1 operating range dc electrical characteristics for commercial grade devices commercial: 0 c t amb +70 c; 4.75v v cc 5.25v symbol parameter min. max. unit v cc supply voltage 2 -0.5 7.0 v v i input voltage -1.2 v cc +0.5 v v out output voltage -0.5 v cc +0.5 v i in input current -30 30 ma i out output current -100 100 ma t j maximum junction temperature -40 150 c t str storage temperature -65 150 c notes: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only. functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. 2. the chip supply voltage must rise monotonically. product grade temperature voltage commercial 0 to +70 c5.0v + 5% industrial -40 to +85 c5.0v + 10% symbol parameter test conditions min. max. unit v il input voltage low v cc = 4.75v 0.8 v v ih input voltage high v cc = 5.25v 2.0 v v i input clamp voltage v cc = 4.75v, i in = -18 ma -1.2 v v ol output voltage low v cc = 4.75v, i ol = 12 ma 0.5 v v oh output voltage high v cc = 4.75v, i oh = -12 ma 2.4 v i i input leakage current v in = 0 to v cc -10 10 a i oz 3-stated output leakage current v in = 0 to v cc -10 10 a i ccq 1 standby current v cc = 5.25v, t amb = 0 c100 a i ccd 1, 2 dynamic current v cc = 5.25v, t amb = 0 c at 1 mhz 3 ma v cc = 5.25v, t amb = 0 c at 50 mhz 75 ma i os short circuit output current 3 one pin at a time for no longer than 1 second -50-200ma c in input pin capacitance 3 t amb = 25 c, f = 1 mhz 8 pf c clk clock input capacitance 3 t amb = 25 c, f = 1 mhz 5 12 pf c i/o i/o pin capacitance 3 t amb = 25 c, f = 1 mhz 10 pf notes: 1. see table 1 on page 7 for typical values. 2. this parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 3. typical values, not tested. ds042.fm page 11 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking ds042 (v1.3) october 9, 2000 www.xilinx.com 12 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. ac electrical characteristics 1 for commercial grade devices commercial: 0 c t amb +70 c; 4.75v v cc 5.25v symbol parameter 71012 unit min. max. min. max. min. max. t pd_pal propagation delay time, input (or feedback node) to output through pal 27.52 10 2 12ns t pd_pla propagation delay time, input (or feedback node) to output through pal & pla 39.53 12 314.5ns t co clock to out (global synchronous clock from pin) 25.52728ns t su_pal setup time (from input or feedback node) through pal 4.5 7 8 ns t su_pla setup time (from input or feedback node) through pal + pla 6.5 9 10.5 ns t h hold time 0 0 0 ns t ch clock high time 3 4 4 ns t cl clock low time 3 4 4 ns t r input rise time 20 20 20 ns t f input fall time 20 20 20 ns f max1 maximum ff toggle rate 2 1/(t ch + t cl ) 167 125 125 mhz f max2 maximum internal frequency 2 1/(t supal + t cf ) 111 80 69 mhz f max3 maximum external frequency 2 1/(t supal + t co ) 957163mhz t buf output buffer delay time 1.5 1.5 1.5 ns t pdf_pal input (or feedback node) to internal feedback node delay time through pal 2 6 2 8.5 2 10.5 ns t pdf_pla input (or feedback node) to internal feedback node delay time through pal+pla 38310.5313ns t cf clock to internal feedback node delay time 4 5.5 6.5 ns t init delay from valid v cc to valid reset 505050 s t er input to output disable 2, 3 91215ns t ea input to output valid 2 91215ns t rp input to register preset 2 11 12.5 15 ns t rr input to register reset 2 11 12.5 15 ns notes: 1. specifications measured with one output switching. see figure 6 and table 6 for derating. 2. this parameter guaranteed by design and characterization, not by test. 3. output c l = 5 pf. ds042.fm page 12 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking 13 www.xilinx.com ds042 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. dc electrical characteristics for industrial grade devices industrial: -40 c t amb +85 c; 4.5v v cc 5.5v symbol parameter test conditions min. max. unit v il input voltage low v cc = 4.5v 0.8 v v ih input voltage high v cc = 5.5v 2.0 v v i input clamp voltage v cc = 4.5v, i in = -18 ma -1.2 v v ol output voltage low v cc = 4.5v, i ol = 12 ma 0.5 v v oh output voltage high v cc = 4.5v, i oh = -12 ma 2.4 v i i input leakage current v in = 0 to v cc -10 10 a i oz 3-stated output leakage current v in = 0 to v cc -10 10 a i ccq 1 standby current v cc = 5.5v, t amb = -40 c125 a i ccd 1, 2 dynamic current v cc = 5.5v, t amb = -40 c at 1mhz 4 ma v cc = 5.5v, t amb = -40 c at 50 mhz 80 ma i os short circuit output current 3 one pin at a time for no longer than 1 second -50-230ma c in input pin capacitance 3 t amb = 25 c, f = 1 mhz 8 pf c clk clock input capacitance 3 t amb = 25 c, f = 1 mhz 5 12 pf c i/o i/o pin capacitance 3 t amb = 25 c, f = 1 mhz 10 pf notes: 1. see table 1 on page 7 for typical values. 2. this parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 3. typical values, not tested. ds042.fm page 13 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking ds042 (v1.3) october 9, 2000 www.xilinx.com 14 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. ac electrical characteristics 1 for industrial grade devices industrial: -40 c t amb +85 c; 4.5v v cc 5.5v symbol parameter 10 15 unit min. max. min. max. t pd_pal propagation delay time, input (or feedback node) to output through pal 2 10 2 15 ns t pd_pla propagation delay time, input (or feedback node) to output through pal + pla 312317.5ns t co clock to out (global synchronous clock from pin) 2728ns t su_pal setup time (from input or feedback node) through pal 88ns t su_pla setup time (from input or feedback node) through pal + pla 10 10.5 ns t h hold time 00ns t ch clock high time 55ns t cl clock low time 55ns t r input rise time 20 20 ns t f input fall time 20 20 ns f max1 maximum ff toggle rate 2 1/(t ch + t cl ) 100 100 mhz f max2 maximum internal frequency 2 1/(t supal + t cf ) 71 69 mhz f max3 maximum external frequency 2 1/(t supal + t co ) 66 63 mhz t buf output buffer delay time 1.5 1.5 ns t pdf_pal input (or feedback node) to internal feedback node delay time through pal 28.5213.5ns t pdf_pla input (or feedback node) to internal feedback node delay time through pal + pla 3 10.5 3 16 ns t cf clock to internal feedback node delay time 66.5ns t init delay from valid v c to valid reset 50 50 s t er input to output disable 2, 3 15 15 ns t ea input to output valid 2 15 15 ns t rp input to register preset 2 15 17 ns t rr input to register reset 2 15 17 ns notes: 1. specifications measured with one output switching. see figure 6 and table 7 for derating. 2. this parameter guaranteed by design and characterization, not by test. 3. output c l = 5pf. ds042.fm page 14 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking 15 www.xilinx.com ds042 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. switching characteristics voltage waveform v cc v in v out c1 r1 r2 s1 s2 component values r1 390 ? r2 390 ? c1 35 pf measurement s1 s2 t pzh open closed t pzl closed closed t p closed closed sp00618 note: for t phz and t plz c = 5 pf, and 3-state levels are measured 0.5v from steady state active level. number of outputs switching 1 2 4 8 12 16 6.0 t pd_pal (ns) 6.2 6.3 6.5 v dd = 5v , 25 c sp00619 6.6 6.7 6.1 6.4 6.8 6.9 7.0 figure 6: t pd_pal vs. outputs switching table 7: t pd_pal vs. number of outputs switching (v cc = 5v, 25 c) number of outputs 12481216 typical (ns) 6.362 6.432 6.49 6.562 6.63 6.705 90% 10% 1.5ns 1.5ns +3.0v 0v t r t f measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. input pulses sp00368 ds042.fm page 15 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking ds042 (v1.3) october 9, 2000 www.xilinx.com 16 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. pin functions and layouts xcr5128c i/o pins function block macrocell vq100 tq128 notes 1123 12-- 1312 14-1 15100128 1699127 17-- 1898126 1997125 110 - - 11196124 112 -122 11394121 11493120 115 - - 11692119 2 1 14 20 22-- 2 3 13 19 24-18 2 5 12 17 2 6 10 15 27-- 28914 29813 210 - - 211712 212 -11 213610 21459(1) 215 - - 21648 3 1 25 36 32-- 3 3 24 32 34-31 3 5 23 30 3 6 22 29 37-- 3 8 21 28 3 9 20 27 310 - - 3111926 312 -24 3131723 3141622 315 - - 3161521(1) 4 1 37 50 42 -- 4 3 36 49 44 -48 4 5 35 47 4 6 33 45 47 -- 4 8 32 44 4 9 31 43 410 - - 4113042 412 -41 4132940 4142839 415 - - 4162738 5 1 40 53 52 -- 5 3 41 54 54 -55 5 5 42 56 5 6 44 58 57 -- 5 8 45 59 5 9 46 60 510 - - 5114761 512 -62 5134863 5144964 515 - - 5165065 6 1 52 67 62 -- 6 3 53 71 64 -72 6 5 54 73 6 6 55 74 67 -- 6 8 56 75 6 9 57 76 610 - - 6115877 612 -79 6136080 function block macrocell vq100 tq128 notes ds042.fm page 16 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking 17 www.xilinx.com ds042 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. (1) jtag pins xcr5128c global, jtag, power, ground, and no connect pins (1) global 3-state pin facilitates bed of nails testing without using logic resources. 6146181 615 - - 6166282(1) 7 1 63 83 72-- 7 3 64 84 74-85 7 5 65 86 7 6 67 88 77-- 7 8 68 89 7 9 69 90 710 - - 7117091 712 -92 7137193 7147294 715 - - 7167395(1) 8175100 82-- 8376101 84-102 8577103 8678104 87-- 8879105 8980106 810 - - 81181107 812 -109 81383110 81484111 function block macrocell vq100 tq128 notes 815 - - 81685112 pin type vq100 tq128 notes in0 87 114 in1 89 116 in2 88 115 in3 90 117 gtsn 88 115 (1) clk0 87 114 clk1 40 53 clk2 37 50 clk3 92 119 tck 62 82 tdi 4 8 tdo 73 95 tms 15 21 vcc 3, 18, 34, 39, 51, 66, 82, 91 7, 25, 46, 52, 66, 87, 108, 118 gnd 11, 26, 38, 43, 59, 74, 86, 95 16, 37, 51, 57, 78, 96, 113, 123 no connects 4, 5, 6, 33, 34, 35, 68, 69, 70, 97, 98, 99 function block macrocell vq100 tq128 notes ds042.fm page 17 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking ds042 (v1.3) october 9, 2000 www.xilinx.com 18 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. 100-pin vqfp 128-pin tqfp sp00485a tqfp 100 76 1 25 75 51 26 50 vqfp sp00469b tqfp 128 1 38 39 65 64 103 102 ds042.fm page 18 monday, october 9, 2000 8:26 pm
r xcr5128c: 128 macrocell cpld with enhanced clocking 19 www.xilinx.com ds042 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. ordering information revision history component availability pins 100 128 type plastic vqfp plastic tqfp code vq100 tq128 xcr5128c -15 i i -12 c c -10 c, i c, i -7 c c example: xcr5128c -7 vq 100 c temperature range number of pins package type speed options -15: 15 ns pin-to-pin delay -12: 12 ns pin-to-pin delay -10: 10 ns pin-to-pin delay -7: 7.5 ns pin-to-pin delay temperature range c = commercial, t a = 0 c to +70 c i = industrial, t a = ? 40 c to +85 c packaging options vq100: 100-pin vqfp tq128: 128-pin tqfp device type speed options date version # revision 9/16/99 1.0 initial xilinx release. 2/10/00 1.1 converted to xilinx format and updated. 8/10/00 1.2 updated figure 3 and pinout table. 10/09/00 1.3 added discontinuation notice. ds042.fm page 19 monday, october 9, 2000 8:26 pm

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